Why Opamp Compensation

OPamp 基本上是所有 analog circuit design 的基礎。不論 amplifier, filter, 以至 bandgap, LDO, ADC 都需要各種不同的 opamp.  Opamp 是 high gain and feedback device, 因此 stability 是非常重要的考慮。Stability 有問題輕則 overshoot or ringing, 重則 oscillate 或 system crash.   Stability 最重要就是靠 compensation.  99% 的 opamp 都是 compensated to unit gain stable.  但也有例外的情況。

1. Some opamp is not fully compensated intentionally.

2. Circuit designer 需要 customized opamp 時。例如 opamp for ADC 或 high bandwidth amplifier 或 filter. 除了 unit gain stable compensation 之外，也可以用本文描述其他的 compensation 技巧。

Dominant Pole Compensation

Dominant pole 大多用於 unit gain stable compensation.  Method 1: 就是大名鼎鼎的 Miller compensation, 歸類於 opamp internal (gain stage) compensation.  利用 gain stage 把 input stage 的 cap 放大 dominant pole, 也就是把上圖的 W push 到更低頻。Non-dominant pole 的位置基本上不變。所以 unit gain frequency 還是維持在 non-dominant pole 的位置 (to be safe, about 1/10 x 1/𝜏2).

Gain Reduction Compensation

Gain reduction compensation 和 dominant pole compensation 有點類似。只是把 gain 拉下來讓 unit gain frequency 變低來增加 phase margin.  比 dominant pole 更糟的是連 gain (含 DC) 都降低，有時會造成 offset 或 DC error 變大。有兩種使用模式。

(i) Gain attenuation 放在 opamp 之後 partial feedback, 實際上是 close loop amplifier 同時增加 phase margin (但減少頻寬以及 gain) 如 figure 13.  (Zg/Zg+Zf).   把 amplifier 和 compensation 結合在一起相當常見，如 OPA643.

(2) Gain attenuation 放在 opamp 之前 between virtue grounds.  可以看到 feedback ratio is reduced to (Rin//Rg) / (Rin//Rg+Rf)  compared with Rg/(Rg+Rf).  不過 close loop gain 仍然是 1+Rf/Rg regardless Rin.

Lead lag compensation 的好處是避免 DC offset or error 因為 opamp DC gain 和維持住。但是 opamp 的 ac 頻寬仍然被犧牲。在需要高速 settling 的應用 ( 如 ADC) 並不是好的 solution.

Lead compensation 的觀念是先 zero 後 pole.  如下圖 zero = 1/RFC;  pole = 1/(RF//RIC).  第一個 zero 基本上 cancel opamp 的 non-dominant pole.  第二個 pole 變成新的 non-dominant pole.  因些新的 system 的頻寬比原來的頻寬大。同時保有原來的 high gain.

Lead and lag compensators are used quite extensively in control. A lead compensator can increase the stability or speed of reponse of a system; a lag compensator can reduce (but not eliminate) the steady-state error.

Consider the first-order compensator shown below.

(1)

The gain (Kd) will be defined as follows so as not to affect the steady-state response.

(2)

The pole (zp) must be a real value inside the unit circle. For a lead compensator, the zero is greater than the pole (zo > zp) and the gain Kd is greater than 1.

Generally for the design of a lead compensator, the zero (zo) is placed close to the location of one of the plant’s poles to achieve an approximate pole-zero cancellation. The compensator pole (zp) is then placed to the left of the zero so that the root-locus will shift to the left. The figure below illustrates how the root-locus shifts by placing the pole and the zero.

Shifting the root-locus to the left results in faster response time.

Lag Compensataor

A first-order phase-lag compensator also can be designed using a frequency response approach. A lag compensator in frequency response form is given by the following.

(9)

The phase-lag compensator looks similar to phase-lead compensator, except that a is now less than 1. The main difference is that the lag compensator adds negative phase to the system over the specified frequency range, while a lead compensator adds positive phase over the specified frequency. A Bode plot of a phase-lag compensator has the following form.

The two corner frequencies are at 1 / T and 1 / aT. The main effect of the lag compensator is shown in the magnitude plot. The lag compensator adds gain at low frequencies; the magnitude of this gain is equal to a. The effect of this gain is to cause the steady-state error of the closed-loop system to be decreased by a factor of a. Because the gain of the lag compensator is unity at middle and high frequencies, the transient response and stability are generally not impacted much.

The side effect of the lag compensator is the negative phase that is added to the system between the two corner frequencies. Depending on the value a, up to -90 degrees of phase can be added. Care must be taken that the phase margin of the system with lag compensation is still satisfactory. This is generally achieved by placing the frequency of maximum phase lag, wm as calculated below, well below the new gain crossover frequency.

(10)

The lag compensator is expressed in the same form as a lead compensator. The general form is repeated below.

(3)

and

(4)

The pole (zp) must again be a real value inside the unit circle. For a lag compensator, however, the zero is less than the pole (zo < zp) and the gain Kd is less than 1.

The philosophy of the design is the following. Consider the root-locus in the figure below as a starting point.

Suppose the root locations za and za_bar give a satisfactory transient response (such as overshoot, settling time, rise time), but that the gain (K) must be increased to reduce the steady-state error. We can add a compensator pole close to z = 1 and a compensator zero to the left of right-most plant pole as shown below.

Recall from your control textbook, the gain K goes to infinity as the closed-loop poles approach open-loop zeros and the gain goes to 0 as the closed-loop poles approach open-loop poles. By adding the compensator zero (zo) to the root-locus, the gain K at za and za_bar increases. Also the compensator zero and pole have been (or should have been) appropriately placed so that the desired root locations za and zabar remain in the same location.