Double Integrator Plant or Controller Application

by allenlu2007

應用面來看 double integrator controller, 參考 Stanford EE392m note

Double integrator plant 的含義是 plant 包含 two integrators (e.g. frictionless mechanics). 配合的 controller 有多種選擇見前文。

另一類問題用包含 double integrator 的 controller 來 track reference (constant, or time varying such as ramp or sinusoidal signal).  主要的原因就是利用 double integrator (i) 反應快 (ii) asymptotical error 趨近 0 的特性。請參考前文1,  2, and 3.

我們先看

Type A: double integrator plant (PD controller 為主,也可以用前文多種 controller)

或類 double integrator plant, two poles close to origins due to friction or finite gain.

但不要和 general two-pole system 混在一起。General two-pole 大多是 one dominant pole + one non-dominant pole, 控制方式可能比較接近 one integrator plant 如下 Type B.

Mechanical Plant

本體包含 double integrators;  因此用 PD controller.

We consider the double integrator plant, which is one of the most fundamental systems in control applications, representing single-degree-of-freedom translational and rotational motion. Applications of the double integrator include low-friction, free rigid-body motion, such as single-axis spacecraft rotation [1] and rotary crane motion [2]. Control of the double integrator has been of interest since the early days of control theory when it was used extensively to illustrate minimum-time and minimum-fuel controllers [3], [4].

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下圖 shows the feedback control system.  有趣的是我們 feedback position error (e = y-yd) and velocity error (e_dot) 而非前文 (double integrator plant control) 的 true position and velocity.  原因是前文最後是最後停在原點 ( both position and velocity).  本文最後是停在 position d and velocity 0.  因此 e=y-yd and e_dot = y_dot. 

另一個差異是 y_dot_dot = u + d,  多了一個 d.  可視為新的外力。換言之原來的外力分解成 state feedback force (u) 加上 state independent force (d).  在沒有外力時 (d=0),  u 最後會接近 0, e 最後也會接近 0.  因些本文的 PD control 其實和前文的 double integrator controller 一樣。

 

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在假設沒有 noise 的情況下,可以把 double integrator 的一個 pole 移往 PD controller.  這時 PD controller 就變成 PI controller.  意即在 one integrator plant 中 (例如 PLL or one pole opamp),最好用 PI controller.  當然在有 noise 的情況下,PD controller 會有 noise amplification 的問題。 

 

Type B:  PLL  (One integrator plant – P controller, PI controller)

Type B 是 one integrator plant.   有兩種情況:

(a) 並非是真的 integrator (pole at origin), 而是 one LHP pole.  如 one pole ideal OPAMP, 或是有 2nd pole 在非常遠的地方 ( pole 位置遠大於unit gain frequency, 通常 10X).  在這種情況下,只要最簡單的 P controller, 就可精準 control plant.  從 root locus 來看,就是 pole 往 negative axis 移動,always stable.

P controller 唯一的缺點,就是反應速度慢。因此另一種方式:

(b) 如果是真的 integrator (pole at origin, e.g. VCO), 或是 one RHP pole.  此時用 P controller 會有 stability 的問題。Wrong statement!  即使 P controller 也是讓 integrator stable.  主要的問題是: (i) response too slow for the 1st order system; (ii) steady state 仍有 error offset or asymptotic to zero (which one?); (iii) 對於 ramp input or acceleration 無法 track (TBC). 

可以用 PI controller ( P+I/s = (I+sP)/s; one pole at origin and one zero; pole frequency < zero frequency).   Based on root locus, close loop with feedback 的 two poles 會 circle LHP zero (如下圖).  一般而言,可以控制 close loop complex poles 有較快的反應且 stable.  同時可以解決 (i) – (iii) 的問題 (TBC?)

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One integrator plant 可以直接用 PD controller 嗎? (P + sD), 乍看之下 close loop with feedback is stable.  是否有其他的問題? 

 

OPamp Compensation/Control

Ideal OPamp 無論是 one integrator (A/s), or one dominant pole (A/s+a), 或是 two poles (one dominant pole, and one high frequency non-dominant pole > 10x of unit gain bandwidth) 一般都用 P controller (resistor divider) 做 control, 既簡單又精確。這也稱為 dominant pole compensation.

如果要對 opamp 做 compensation, 有幾點和傳統 PID controller 不同。(1) CMOS 電路的特性是容易產生 pole. (電流流過並聯的 R//C, pole 的位置在 1/(2piRC)). pole/I 位置多半不在原點; (2) Opamp 的頻寬高,不大可能用普通的 PID controller 來做 compensation. 而是用 RLC passive component 做 compensation.

(1) 可能可以用 dominant pole shift to origin 來解決。 (2) RLC 是雙向而非單向,多半有附帶的 loading effect pole/zero.  E.g. 很難產生 zero only, 一般是 zero and pole pair (I 流過串聯 R and C, pole 在 origin, zero 在 1/(2piRC)).  如下圖所示。 另外在做 capacitive feedback 時,很容易產生  feedforward zero.  

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如何 link PID controller or RLC netlist, with matrix formation(?)  見 double integrator plant control 文。Two poles, miller compensation, nested miller, etc.  應該可行但沒有 physical insight.

 

在 opamp 內部電路大多是 cascade (串接) 兩個或三個 one pole stage.  以 two poles 為例,如果 two poles 位置能讓 non-dominant pole > 10X of unit gain frequency.  這個 opamp 基本上 stable 不需要 compensation.  如果需要 control (amplify or actuator) 可以用最簡單的 P controller.

 

如果 non-dominant pole 位於 unit gain frequency 內,但和 dominant pole 仍有距離 ( > 10X of the dominant pole frequency), 可以用 (1) gain reduction compensation (flat attenuation, P controller, sort of); (2) lag compensation (only attenuate high frequency (PI controller?); and (3) lead-lag compensation (PI controller)

 

更困難的 case 是 two pole 非常接近或相同。基本上就和 double integrators 類似,需要更複雜的 controller.  最常見的就是 Miller compensation (就是 make two poles –> pole splitting).  除此之外,是否有更好的 compensator?   Pole splitting sacrifices the gain at higher bandwidth and speed.

Yes, two pole compensation.  lead compensation (???)

 

幾種常見的 compensation: Miller compensation, PI compensation (lead-lag?), two pole compensation

另外常見在 feedback 電路如果有 capacitor, 除了多了 feedback pole 之外,同時多了 feedforward RHP zero.

E.g. Miller compensation

Miller compensation (pole splitting and plus zero compensation)

lead compensation (add zero)

 

以上都是用古典 PID controller 方式,可以對比 matrix 方式 (如 double integrator reachability and stability)?

 

Sigma Delta Modulator (SDM)

CIFF:  every integrator output feedforward

CIFB:  every integrator input feedback

 

DC-DC converter (類 double integrator plant)

我最有興趣的是如何用在 DC-DC converter, because it consists of inductor, capacitor, and resistor.  

基本的 DC-DC buck converter block diagram 如下。

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以下是定量的分析。

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另一篇 TI 的 AP note 也是很好的參考。

Based on (4), -[UR(t)+1/K Ug(t)] 和 Uref 的比較決定 switch 的開或關。如果 UR(t) 比較低,switch short 的 duty cycle 提高拉昇 UR(t).  反之如果 UR(t) 比較高,switch short 的 duty cycle 降低拉低 UR(t). 最後 UR(t) 會在 Uref 附近抖動。主要靠 output C 減小 UR(t) 的抖動。

下圖的 Vramp = Ug(t); Vcontrol = Ucomp; Vmod = a

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包含 compensation circuit 如下圖。   

 

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相對應的 close loop diagram 如下 (從 Vref 出發,而非 Vin or Uo 出發):

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先看每一個 block transfer function.  

 

Hmod(s) 如前所述只是一個 constant gain (with some negligible phase shift) 把 error signal 放大 (both voltage and current).  類似 PLL 的 phase detector and charge pump.  之後的 filter 也可以想成是 loop LPF.  

 

接下來是 Hfilter(s):

假設 LC 都是 ideal component. 

Hfilter(s) = Hrlc(s).   當 R 很大時趨近 double integrators.  一般是 two poles 在 LHP.  

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如果包含 parasitic resistance, Hfilter(s) 如下。還有更複雜的 loading model 以及 modulator operation mode (CCM or DCM).  在此先不討論。

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Compensator 如下。是 2-poles and 2-zeros compensator.

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sliding mode control

 

 

Type B:  PLL  (One integrator plant + PI controller)

Why not multi-integrator?

two pole is fundamental, right?  polynomial factoring (one pole or two conjugated poles) => cascaded plants

But multi-poles plant/filter/controller do exist (e.g. sigma delta): always decompose to cascaded one pole or two poles plant? 

cascaded plant (串聯). How about parallel plant (並聯) for two poles or multi-poles?

cons:  matching!  amplitude matching; phase (delay) matching ==> very difficult to analyze stability !

no signal multiplication but signal addition or selection/switching (not good for small signal) 

Cons: distortion at cross-over point (class B)

 

How about Pros?

* Robust:  in cascaded system, one plant fails mean all fails.  Sometimes, not even fail, just saturation causes the entire system fail.  (e.g.  CIFB vs. CIFF in sigma delta modulator)

* High dynamic range:  (i) no cascaded gain, each plant has the same dynamic range;  (ii) control some plant (high Q) to saturate first to increase dynamic range)

* Most attractive:  noise cancellation (but be careful not signal cancellation: by out of frequency or operation band (hmos or pmos only for positive/negative signal), or inner loop (like chopper or cross coupling feedback));  offset cancellation (chopper)

* Stability seems to be better if control each path 2nd pole.

* Low latency; fast response

 

 

 

 

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